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Description: I used code verilog. Synchronous dynamic random access memory (SDRAM) is dynamic random access memory (DRAM) that is synchronized with the system bus. Classic DRAM has an asynchronous interface, which means that it responds as quickly as possible to changes in control inputs. SDRAM has a synchronous interface, meaning that it waits for a clock signal before responding to control inputs and is therefore synchronized with the computer s system bus. The clock is used to drive an internal finite state machine that pipelines incoming commands. The data storage area is divided into several banks, allowing the chip to work on several memory access commands at a time, interleaved among the separate banks. This allows higher data access rates than an asynchronous DRAM
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Size: 28672 |
Author: thuanbk |
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Description: 基于Verilog,SDRAM的读写控制和Modelsim仿真。-Based Verilog, SDRAM read and write control and Modelsim simulation.
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Size: 9216 |
Author: heyun |
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Description: DDR2 SDRAM Control Verilog RTL Code
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Size: 312320 |
Author: richman |
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Description: Generic Wishbone R3 compliant SDRAM controller written in Verilog
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Size: 10240 |
Author: corgano |
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Description: SDRAM的仿真模型Verilog。用于美光mt48lc32m16a2，可在ModelSim下用。-Simulation Model of SDRAM
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Size: 6144 |
Author: zhang mr |
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Description: 基于FPGA的读写控制，sdram，简单易懂，verilog代码描述-FPGA-based read and write control, sdram, easy to understand, verilog code Description
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Size: 10240 |
Author: 张红玉 |
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Description: 本源码由Verilog语言编写，用硬件实现SDRAM的读写和存储数据功能，包括SDRAM的控制模块、初始化模块、读写模块等！-The source the Verilog language, implemented in hardware SDRAM read and write and store data, including SDRAM control module, initialization module, reader module, etc!
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Size: 3072 |
Author: zhanglong |
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Description: 基于SDRAM的读写调试试验，使用verilog语言编写，经过调试。-SDRAM-based literacy commissioning tests, using verilog language, through debugging.
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Size: 2285568 |
Author: jianglei |
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Description: SDRAM的verilog描述，包含顶层设计，测试平台代码，精确描述-SDRAM is verilog description, including top-level design, testbench code, an accurate description of
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Size: 6144 |
Author: micheal zhang |
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Description: 基于FPGA的SDRAM串口实验，verilog语言写的，附件里是做实验的工程，连上串口，下进去就有数据了，波特率9600，一个停止位，SDRAM时钟是96MHz，数据时FPGA自动产生的，正确输出结果是00到FF递增一，再循环。这个工程警告比较少，基本是故意为之的警告，时序也已经收敛。-FPGA-based SDRAM serial experiments, verilog language written annex is to do the experiment works, even on the serial port, the data will have to go under, 9600 baud, one stop bit, SDRAM clock is 96MHz, automatically generated data FPGA the correct result is output to the FF 00 is incremented by one, recycle. The project is relatively small warning, a warning is intentionally basic timing also has converged.
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Size: 5591040 |
Author: Grace |
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Description: 使用FPGA实现SDRAM逻辑控制器，适用于各种型号的FPGA-SDRAM control by verilog
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Size: 204800 |
Author: 贾先生 |
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Description: 使用ALTERA的FPGA控制SDRAM的verilog程序-Use ALTERA s FPGA to control SDRAM s verilog program
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Size: 13050880 |
Author: 李 |
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Description: 均值滤波是典型的线性滤波算法，（Verilog HDL）设计所需的模块有：
（1）带PLL的全局时钟管理模块 system_ctrl_pll.v
（2）OV7725 COMS Sensor的初始化模块 i2c_timing_ctrl、I2C_OV7725_RGB565_Conofig
（3）OV7725 COMS Sensor的视频信号采集模块COMS_Capture_RGB565
（4）SDRAM数据交互控制器Sdram_Control_2Port
（5）VGA时序驱动电路lcd_driver
-Design the required modules are:
(1) global with PLL clock management module system_ctrl_pll. V.
(2) the OV7725 COMS i2c_timing_ctrl initialization module, I2C_OV7725_RGB565_Conofig Sensor
(3) the OV7725 COMS Sensor COMS_Capture_RGB565 video signal acquisition module
(4) SDRAM controller data interaction Sdram_Control_2Port
(5) the VGA timing drive circuit lcd_driver
逐句翻译
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Size: 8895488 |
Author: Keyonwho |
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Description: 文件里有DDR3/DDR4 sram的verliog模型，而且具有DDR4参考书(The document has a verliog model of DDR3/DDR4 SRAM, and it has DDR4 reference books.)
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Size: 4935680 |
Author: maxw123456789 |
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